1. Field of the Invention
The present invention generally relates to a circuit for generating a data strobe signal of a semiconductor memory device, and more specifically, to a technology of regulating a tDQSS margin depending on change of an operating frequency tCK in response to a CAS latency signal.
2. Description of the Related Art
A synchronous DRAM (hereinafter, referred to as “SDRAM”) which is operated synchronously with respect to an external system clock has been developed to improve an operating speed of a DRAM. Additionally, a Rambus DRAM and a double data rate (hereinafter, referred to as “DDR”) SDRAM for processing data synchronously with respect to rising and falling edges of one clock have been also developed to further improve the operating speed of the data.
In case of the DDR SDRAM, a source synchronous interface is used because data are transmitted at a high speed. Here, input/output operations of the data are performed synchronously with respect to a data strobe signal (hereinafter, referred to as “DQS”) at a data source.
FIG. 1a is a timing diagram of a conventional clock CLK and conventional data strobe signals DQS1 and DQS2.
At a JEDEC standard, tDQSS of DDR1 (time from a rising edge of the clock to a first rising edge of the data strobe signal) is defined as 0.75*tCK˜1.25*tCK, and tDQSS of DDR2 is defined as WL (Write Latency: time from input of a write command to input of data) −0.25*tCK˜WL+0.25*tCK.
Hereinafter, the data strobe signal and a tDQSS margin will be explained using an example of DDR1. As mentioned above, in case of the DDR1, a falling edge of the data strobe signal DQS ranges from 0.75*tCK to 1.25*tCK, that is, the data strobe signal has a margin of 0.5*tCK.
FIG. 1b is a diagram illustrating data latched by the data strobe signals of FIG. 1a. 
A skew between the data strobe signals is represented by tDQSS. The fastest data strobe signal DQS1 can be enabled after 0.75tCK from the write command, and the latest data strobe signal DQS2 is enabled after 1.25tCK from the write command. In other words, one data strobe signal is not constantly inputted at the same timing whenever a write operation is performed but fast or late inputted depending on change of peripheral environment.
In this case, data arranged by each data strobe signal have skews of 0.5tCK, respectively.
As a result, the latest data of data inputted by a first write command should latched not by a control signal of a clock domain but by the data strobe signal before the fastest data of data inputted by a second write command is enabled.
The data arranged by the data strobe signals have a timing margin of 0.5tCK in a domain cross portion (where data are transited from a data strobe domain to a clock domain), and a value of tDQSS has a setup/hold margin of 0.25tCK.
However, it is difficult to secure a sufficient tDQSS margin at tCK of all operating frequencies because a value of tCK is differentiated depending on an operating frequency of the memory.
FIG. 2 is a diagram illustrating a conventional circuit for generating a data strobe signal.
The conventional circuit for generating a data strobe signal comprises inverters IV1 and IV2, a delay unit 10, a NAND gate ND1 and a pulse generating unit 20.
The inverter IV1 inverts an internal clock signal ICLK, and the inverter IV2 inverts a data latch control signal DLC. Here, the internal clock signal ICLK to delay an external clock signal CLK is a clock signal which is a basis of the internal operation, and the data latch control signal DLC is a control signal to latch data inputted externally at the write operation.
The delay unit 10 delays an output signal from the inverter IV1. Here, the value of tDQSS is regulated depending on a delay time of the delay unit 10, and the delay unit 10 previously set the delay time.
The NAND gate ND1 performs a NAND operation on output signals from the inverter IV2 and the delay unit 10.
The pulse generating unit 20 outputs a data strobe signal DSTB having a pulse in response to an output signal from the NAND gate ND1. That is, the pulse generating unit 20 generates a pulse signal having a width corresponding to an internally designated delay when the internal clock signal ICLK transits to ‘high’.
In the above-described conventional circuit for generating the data strobe signal, as shown in FIG. 3, the data strobe signal DSTB is enabled to ‘low’ when the internal clock signal ICLK is applied and the data latch control signal DLC is enabled to ‘low’. That is, while the data latch control signal DLC is at the low level, the data strobe signal DSTB is generated.
As a result, since the value of tDQSS is regulated depending on the delay time determined in the delay unit 10 regardless of change of the tCK resulting from the change of the operating frequency, it is difficult to secure the sufficient tDQSS margin when the operating frequency is change to cause change of the tCK.